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SN74LVC2G74DCUR 10 μA Max ICC Programmable Logic ICS Flip Flops Positive Edge Trig

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SN74LVC2G74DCUR 10 μA Max ICC Programmable Logic ICS Flip Flops Positive Edge Trig

China SN74LVC2G74DCUR 10 μA Max ICC Programmable Logic ICS Flip Flops Positive Edge Trig supplier

Large Image :  SN74LVC2G74DCUR 10 μA Max ICC Programmable Logic ICS Flip Flops Positive Edge Trig

Product Details:

Brand Name: TI
Model Number: SN74LVC2G74DCUR

Payment & Shipping Terms:

Minimum Order Quantity: Contact us
Price: Contact us
Packaging Details: VSSOP8
Delivery Time: The goods will be shipped within 3 days once received fund
Payment Terms: Paypal, Western Union, TT
Supply Ability: 50000 Pieces per Day
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Detailed Product Description
Supply Voltage - Min: 1.65 V Supply Voltage - Max: 5.5 V
Minimum Operating Temperature: - 40 C Maximum Operating Temperature: + 125 C
Mounting Style: SMD/SMT Package / Case: VSSOP-8

SN74LVC2G74DCUR Programmable Logic ICS Flip Flops Positive Edge Trig

 

1 Features

  • Available in the Texas Instruments NanoFreeTM Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Maxtpd of5.9nsat3.3V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8VatVCC =3.3V,TA =25°C
  • Typical VOHV (Output VOH Undershoot) >2VatVCC =3.3V,TA =25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
  • – 2000-V Human-Body Model
  • – 200-V Machine Model
  • – 1000-V Charged-Device Model

 

2 Applications

  • Servers
  • LED displays
  • Network switch
  • Telecom infrastructure
  • Motor drivers
  • I/O Expanders

 

3 Description

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Device Information

PART NUMBER

PACKAGE

BODY SIZE

SN74LVC2G74

SM8 (8)

2.95 mm × 2.80 mm

VSSOP (8)

2.30 mm × 2.00 mm

DSBGA (8)

1.91 mm × 0.91 mm

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